1. Field of the Invention
The present invention relates to a method for making a through-silicon via structure. In particular, the present invention relates to a method for making a through-silicon via structure with a protection ring.
2. Description of the Prior Art
The through-silicon via technique is a novel semiconductor technique. The through-silicon via technique mainly resides in solving the problem of the electrical interconnection of chips and belongs to a new 3D packing field. The hot through-silicon via technique creates the products which much more meet the market trends of “light, thin, short and small” by the 3D stacking through the through-silicon via to provide the micro electronic mechanic system (MENS), the photoelectronics and electronic elements with packing techniques of wafer-level package.
The through-silicon via technique drills holes in the wafer by etching or laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. Finally, the wafer or the dice is thinned to be stacked or bonded together to be a 3D stack IC. In such way, the wire bonding procedure may be omitted. Using etching or laser to form conductive vias not only omits the wire bonding but also shrinks the occupied area on the circuit board and the volume for packing. The inner connection distance of the package by the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, compared with the conventional stack package of wire bonding type, the 3D stack IC has much shorter inner connection distance, so the 3D stack IC performs better in many ways, such as faster transmission, and lower noise. Especially for the CPU, flash memory and memory card, the advantages of the shorter inner connection distance of the through-silicon via technique are much more outstanding. In addition, the package size of the 3D stack IC equals to the size of the dice, so the through-silicon via technique is more valuable in the portable electronic devices.
For the current process and techniques, the through-silicon via technique may divided into two types, namely the via first or the via last. The via first process further includes two variations, called before CMOS and after CMOS. In the via-first-before-CMOS process, through-silicon holes are formed on the silicon wafer and filled with a conductive material before the formation of the CMOS. Considering the high temperature procedures in the later CMOS process, the selection of the conductive material is basically focused on those which can bear high temperatures, such as poly silicon, rather than the better copper. To be viewed as a whole, the via-first-before-CMOS process is more compatible with the conventional CMOS process. However, the conductive material must bear high temperatures.
In the via-first-after-CMOS process, the formation of the via and the filling of the conductive metal are done after the completion of the CMOS process. The current conductive metal is copper, which is a better choice than poly silicon in conductivity concern. Because the filling of copper may fail due to the formation of void, tungsten may be an alternative choice. To be viewed as a whole, the filling of copper is particularly difficult because the CMOS is completed, which makes it less compatible with the conventional CMOS process.
Given the above, a novel method to make a novel through-silicon via structure is still needed. In this novel method, copper has the chance to replace the less conductive poly silicon in the through-silicon via structure. In addition, the completion of the CMOS will not hinder the planarization of the copper after the filling of copper.